1. Field of the Invention
The present invention relates to an optimum clock generator in a data receiver, particularly suitable for generating, for example, a PN code clock for a PN code generator of a spectrum spread (SS) communication receiver.
2. Related Art
SS communications are widely used in satellite communications and the like because of its effective reduction in transmission power. In an SS communication, at the transmitting side, communication data are modulated and, thereafter, spread with a fast PN code (pseudo noise code) to generate a wide band SS signal which is emitted in air as radio waves. At the receiving side, on the other hand, the wide band SS signal is despread with a PN code in synchro with the spread PN code and, thereafter, demodulated with a demodulator into the original communication data.
According to the information theory, an S/N ratio and the bandwidth are exchangeable so that less power is required to transmit a certain amount of information.
The structure of a receiving unit of a conventional SS receiver is shown in FIG. 1.
Referring to FIG. 1, an SS received signal is inputted to a correlation detector 10 where it is correlated with two PN codes different in phase outputted from a PN code generator 12 and then detected. Connected to the output side of the correlation detector 10 is a controller 14 where a difference between two correlated detection outputs is calculated by a subtracter and passed to a low-pass filter LPF to generate a control voltage.
Connected to the output side of the controller 14 is a voltage-controlled oscillator VCO 16 which oscillates at a frequency corresponding to the control voltage. Thus, VCO 16 generates clocks in synchro with the SS received signal, which clocks are supplied as PN code clocks to the PN code generator 12 connected to the output side of VCO 16.
The correlation detector 10, controller 14, VCO 16 and PN code generator 12 constitute a so-called Delay Lock Loop (DLL).
The PN code generator 12 generates a PN code for despreading and PN codes for the correlation detector 10, in response to the PN code clock.
The PN code for despreading is supplied to a mixer 18 where it is mixed with the SS received signal to generate a despread signal (e.g., BSPK wave). Connected to the output side of the mixer 18 is a costae circuit 20 where the original base band data are demodulated from the BPSK wave.
At the time immediately after the receiver starts its operation, there is no synchronization between the PN code on a radio wave from the transmitter and the PN code for despreading generated by the PN code generator 12, so that the DLL is not still locked in and a despread signal is not generated.
In view of the above point, at the time immediately after the receiver starts its operation, the SS received signal is inputted to a correlator 22 to detect a frame synchronization signal within the SS received signal, i.e., that portion of a simple PN code train without data, and output a synchronization signal detection signal (negative pulse).
The timing when the correlator 22 outputs the synchronization signal detection signal is a predetermined time before the data start position within a single frame of the SS received signal. Thus, when the correlator 22 outputs a synchronization signal detection signal, a counter 24, for example of a leading edge active type, is reset and thereafter it is caused to count the output clocks from VCO 16 at each leading edge thereof (namely, the leading edge of a clock is active relative to the counter 24). When the counter 24 counts a predetermined number of clocks, it outputs a reset signal to the PN code generator 12 to thus obtain initial synchronization of the PN code.
With the above conventional technique, however, there is no synchronization between the synchronization signal detection signal outputted from the correlator 22 and the output clock from VCO 16, so that the timing when the counter 24 counts a first clock after it was reset fluctuates within one clock duration at a maximum.
Accordingly, the timing when the PN code generator 12 is reset also fluctuates. Thus, after the initial synchronization, the PN code for despreading may be displaced from the PN code of the PN received signal. As a result, the lock-in of the DLL may take some timer or fail so that the correct demodulation of data delays or fails.
In consideration of the above problems, the present invention seeks to provide an optimum clock generator in a data receiver capable of reducing the fluctuation of time when the clock becomes active after the synchronization signal was received from the PN received signal to thus allow a more reliable operation of the data receiver.